728x90
반응형
아무 생각 없이 잘못 짠 것 같습니다. 작동은 되나?
- 테스트 벤치 결과 잘 됩니다.
아래 첨부
code:
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/03/11 13:40:54
// Design Name:
// Module Name: full_subtractor_2
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module full_subtractor_2(x, y, b_in, b_out, d);
// I/O port declarations
input x, y, b_in;
output b_out, d ;
// specify the function of a full subtractor
assign #5 {b_out, d} = x - y - b_in;
endmodule
testbench Code:
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/03/11 13:55:39
// Design Name:
// Module Name: sim_2
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sim_2;
reg x, y, b_in;
wire b_out, d;
// Instantiate the full subtractor
full_subtractor_2 FS2 (
.x (x),
.y (y),
.b_in (b_in),
.b_out (b_out),
.d (d)
);
reg [5:0] i;
initial begin
for (i=0; i<=63; i=i+1) begin
x = i[5:4];
y = i[3:2];
b_in = i[1:0];
#20;
end
#6000
$finish;
$monitor($realtime, "ns %b %b %b %b %b", x, y, b_in, b_out, d);
end
endmodule
728x90
반응형
'Verilog HDL > 2. Verilog Practice (연습)' 카테고리의 다른 글
[full_subtractor] 4. Mixed Modeling (0) | 2024.03.11 |
---|---|
[full_subtractor] 3. Behavioral Modeling (0) | 2024.03.11 |
[full_subtractor] 1. Structural Modeling (0) | 2024.03.10 |
[Verilog] SPI Master 구현 (0) | 2024.01.31 |
[Verilog] Counter를 이용한 LED 제어 구현 (0) | 2024.01.31 |