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Code:
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/03/10 22:49:18
// Design Name:
// Module Name: full_subtractor_1
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
// Full Subtractor in Structural Modeling
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module half_subtractor_1(x, y, b, d);
input x, y ;
output b, d ;
// half subtractor body
// instantiate primitive gates
xor (d, x, y) ;
and (b, ~x, y) ;
endmodule
module full_subtractor_1 (x, y, b_in, b_out, d);
input x, y, b_in ;
output b_out, d ;
wire b1, b2, d1 ;
// full subtractor body
// instantiate the half subtractor
half_subtractor_1 hs_1 (x, y, b1, d1);
half_subtractor_1 hs_2 (d1, b_in, b2, d);
or (b_out, b1, b2);
endmodule
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