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Verilog HDL/1. Verilog HDL Basic (문법)

[Using the Always Block] 4. 예제 풀이

by 한PU 2024. 1. 10.
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1. continuous assignment 와 procedural blocks의 차이점은?

 

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We use procedural blocks such as the always block to execute code sequentially in verilog. In contrast, continuous assignment is executed in parallel.

 

2. 왜 Sensitivity lists를 always block 에서 사용하나?

 

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They define the list of signals that an always will wait on before resuming the execution of code.

 

3. blocking 과 non-blocking 할당의 차이점은?

 

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When we use blocking assignment all signal assignments take effect immediately. In contrast, when we use non-blocking assignment our signals are updated using assignment scheduling.

 

4. continuous 할당에서 어떤 type의 할당을 사용할 수 있나? procedural blocks에서는?

 

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- When we write code using continuous assignment, we can only use blocking assignment.


- We can use both types of assignment within a verilog procedural block. However, non-blocking assignment normally results in a sequential implementation after synthesis. In contrast to this, blocking assignment normally results in a combinational implementation.

 

5. 4 input NAND를 always block으로 설계

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always @(*) begin
	nand_out = ~ (a & b & c & d);
end

 

6. 아래 그림의 코드 작성

counter

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always @(posedge clock) begin
	q_dff1 <= (q_dff2 | q_dff3);
	q_dff2 <= q_dff1;
	q_dff3 <= q_dff2;
end

 

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