1. parameterized modules의 장점은?
We can configure the functionality of the module when we instantiate it. This allows us to make our code easier to reuse.
2. generate block은 어떤 용도로 사용하는가?
We use them to control the way that our designs are compiled and built. They allow us to conditionally include blocks of code in our design at compilation time.
3. for loop와 generate for block의 차이점은?
The generate for block is evaluated at compile time, meaning only one branch of the code block is ever compiled. All the code of a for loop is compiled and it is evaluated continuously during simulations.
4. 16bit 동기식 카운터 2개를 인스턴스화하는 generate for block을 작성하시오.
- 두 카운터는 parameterized module 예제를 사용하시오.
genvar i;
wire [15:0] count_out [1:0]
generate
for (i = 0; i < 2; i = i + 1) begin
counter # (
.BITS (16)
) count_12 (
.clock (clock),
.reset (reset),
.count (count_out[i])
);
end
endgenerate
5. parameter 값에 따라 8bit 카운터 또는 16bit 카운터를 인스턴스화하는 generate block을 작성하시오.
- if 구문, case 구문중 하나를 택할 수 있음.
parameter COUNT_16 = 0;
// case
generate
case (COUNT_16)
0 : begin
counter # (
.BITS (16)
) count_16 (
.clock (clock),
.reset (reset),
.count (count16_out)
);
end
default : begin
counter # (
.BITS (8)
) count_8 (
.clock (clock),
.reset (reset),
.count (count8_out)
);
end
endcase
endgenerate
// if문
generate
if (COUNT_16) begin
counter # (
.BITS (16)
) count_16 (
.clock (clock),
.reset (reset),
.count (count16_out)
);
end
else : begin
counter # (
.BITS (8)
) count_8 (
.clock (clock),
.reset (reset),
.count (count8_out)
);
end
endgenerate
'Verilog HDL > 1. Verilog HDL Basic (문법)' 카테고리의 다른 글
[Verilog Tutorial] level-10 Reusable Code 모음 (0) | 2024.01.16 |
---|---|
[Reusable Code] 2. 생성문 (0) | 2024.01.16 |
[Reusable Code] 1. 매개변수 (0) | 2024.01.16 |
[Verilog Tutorial] level-9 Function and Task 모음 (0) | 2024.01.16 |
[Function and Task] 3. 예제 풀이 (0) | 2024.01.16 |