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HW Design/1. Verilog HDL Basic

[Reusable Code] 3. 예제 풀이

by 한PU 2024. 1. 16.
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1. parameterized modules의 장점은?

 

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We can configure the functionality of the module when we instantiate it. This allows us to make our code easier to reuse.

 

2. generate block은 어떤 용도로 사용하는가?

 

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We use them to control the way that our designs are compiled and built. They allow us to conditionally include blocks of code in our design at compilation time.

 

3. for loop와 generate for block의 차이점은?

 

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The generate for block is evaluated at compile time, meaning only one branch of the code block is ever compiled. All the code of a for loop is compiled and it is evaluated continuously during simulations.

 

4. 16bit 동기식 카운터 2개를 인스턴스화하는 generate for block을 작성하시오.

- 두 카운터는 parameterized module 예제를 사용하시오.

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genvar i;

wire [15:0] count_out [1:0]

generate
	for (i = 0; i < 2; i = i + 1) begin
		counter # (
			.BITS (16)
		) count_12 (
			.clock    (clock),
			.reset    (reset),
			.count    (count_out[i])
		);
	end
endgenerate

 

5. parameter 값에 따라 8bit 카운터 또는 16bit 카운터를 인스턴스화하는 generate block을 작성하시오.

- if 구문, case 구문중 하나를 택할 수 있음.

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parameter COUNT_16 = 0;

// case
generate
	case (COUNT_16)
		0 : begin
			counter # (
				.BITS (16)
			) count_16 (
				.clock    (clock),
				.reset    (reset),
				.count    (count16_out)
			);
		end
		default : begin
			counter # (
				.BITS (8)
			) count_8 (
				.clock    (clock),
				.reset    (reset),
				.count    (count8_out)
			);
		end
	endcase
endgenerate

// if문
generate
	if (COUNT_16) begin
		counter # (
			.BITS (16)
		) count_16 (
			.clock    (clock),
			.reset    (reset),
			.count    (count16_out)
		);
	end
	else : begin
		counter # (
			.BITS (8)
		) count_8 (
			.clock    (clock),
			.reset    (reset),
			.count    (count8_out)
		);
	end
endgenerate
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